Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs essentially only a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. Nos. 3,811,076 by W. M. Smith and 3,841,926 by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one-device field effect transistor memory cell of the type described in the above-identified Dennard patent which is made to a small size by utilizing a layer of doped polycrystalline silicon separated by a dielectric medium disposed on the surface of a semiconductor substrate for forming a storage capacitor.
In commonly assigned U.S. Pat. No. 3,979,734, filed June 16, 1975, by W. D. Pricer and J. E. Selleck, there is described a memory array made of small cells which employ storage capacitors and bipolar transistors. In this array, each storage capacitor of these cells has simply one capacitor terminal or plate connected to a separate bit/sense line while selected cells forming a word are simultaneously accessed by utilizing a word pulse for coupling to the other terminal or plate of the storage capacitors of that word.
In another commonly assigned U.S. Pat. No. 4,080,590, filed Mar. 31, 1976, by W. D. Pricer, there is disclosed a merged charge memory produced in a unipolar technology which is provided with very small capacitor cells, each of which includes substantially only a small storage capacitor having a bit/sense line connected to one terminal of the capacitor and a word line providing a coupling to the other terminal of the capacitor. In an embodiment of that invention, a direct current source of charges is produced at the surface of a semiconductor substrate and a plurality of inversion storage capacitors are formed also at the surface of the semiconductor substrate in a spaced-apart relationship from the charge source. Voltage pulses representing binary digits are applied to one terminal of the capacitors and the other terminal of the capacitors is coupled to the direct source of charges by the application of a word pulse to a word line.
In yet another commonly assigned U.S. Pat. No. 4,040,017, filed Mar. 31, 1976, by H. S. Lee, there is disclosed a capacitor memory similar to that disclosed in the above-identified U.S. Pat. No. 4,080,590 wherein the charges are produced from a charge source in the form of pulses injected into the storage capacitors rather than by utilizing a direct current source of charges.
Semiconductor memories have generally been accessed in what is known as a two-dimensional accessing arrangement wherein a single word line controls a number of memory cells with each cell having a bit/sense line connected to input/output or control circuitry. However, it is known in the prior art that the input/output or control circuitry may be coupled to more than one bit/sense line to provide certain space saving advantages which may be required for sense amplifiers when very small cells of the above described type are used. Such accessing arrangements are at times referred to as a 21/2 dimensional operation.
In commonly assigned U.S. Pat. No. 4,160,275, filed on Apr. 3, 1978, by H. S. Lee, W. D. Pricer and N. G. Vogl, Jr., there is disclosed an accessing arrangement wherein the minimum pitch of a sense amplifier may be several times the dimension of the desired or optimum bit line pitch of a merged charge memory array by selecting at one time only a small number of cells, such as a byte, associated with a word line for writing or reading purposes.